1. Field of the Invention
This invention relates to a method of fabricating a trench capacitor cell for a semiconductor device, and more particularly to an improved method of fabricating a trench capacitor cell suitable for a dynamic MOS memory device.
2. Description of the Prior Art
In order to show the background of the invention, a typical prior art process for making a trench capacitor cell is illustrated in FIGS. 3A-3F.
Referring first to FIG. 3A, the capacitor cell fabrication starts with anisotropically etching a trench 1a in a semiconductor substrate 1 of one conductivity type. An oxide layer 2 is deposited on the upper surface of the substrate including the walls of the trench 1a by means of thermal oxidation, and then, a contact hole or opening 2a is made in the oxide layer 2. Through the opening 2a, impurity ions of the conductivity type opposite the substrate are implanted to create a diffusion region 4. Subsequent to the ion implant, a polysilicon layer 3 of the conductivity type opposite the substrate is applied over the oxide layer 2.
In FIG. 3B, a resist 5 is shown positioned over the substrate 1 and filling the trench 1a. The resist 5 is then patterned by a mask and etch process to expose the trench 1a as shown in FIG. 3C. In the next step, using the resist 5 as the mask, anisotropical etching is carried out on a polysilicon layer 3 to remove only the portion thereof lying at the bottom of the trench (FIG. 3D). After the anisotropic etching, the resist 5 is entirely stripped (FIG. 3E). A relatively thin layer of oxide 6 is developed on the polysilicon layer 3. Another polysilicon layer 7 covers the oxide layer 6 and fills the trench as shown in FIG. 3F, thereby completing a trench capacitor cell which stores charge between the two polysilicon layers 3 and 7.
One problem of the prior art fabricating process discussed above is that the resist 5 fills the trench 1a and form a plug-like downward extension 5a far greater in vertical dimension than the rest of the resist 5 as shown in FIG. 3B. When the resist 5 is masked and etched by photolithography to form an opening over the trench 1a through which subsequent anisotropic etching is performed, the plug-like extension 5a of the resist can not be completely removed, leaving its remnants within the trench. When anisotropic etching is performed to remove the polysilicon layer 3 from the trench bottom, the oxide remnants within the trench have an adverse effect of retarding the anisotropic etching action on the polysilicon. As a result, the complete removal of the polysilicon from the trench bottom, thus the complete trench isolation of the device is not successfully effected.